The action procedures for a logic gate use the current input signals to compute
a new output signal which is set after a delay by adding the change to the
agenda. The agenda proedures run in FIFO order to ensure the last procedure to
set the signal of a wire for a specific point in time is setting a signal which
incorporates all the changes in input signals rather than an incomplete subset
of changes.

Example:
Consider an and gate with inputs 0, 1 which change to 1, 0 at the same time.
WLOG assume the action procedure for the left wire runs first.
- The left wire's procedure will set its input so the wires have signals 1, 1
 and add "set output 1" to the agenda.
- The right wire's procedue will run setting the right input signal so the
  wires have signals 1, 0 and adding "set output 0" to the agenda.
If LIFO order is used the final output signal will incorrectly be 1.

FIFO is sufficient but not necessary.
Example: And gate with 3 input changing from 0, 0, 1 to 1, 1, 0.
Assume the action procedures for the wires are run left to right. The execution
order can be 1st, 2nd, 3rd or 2nd, 1st, 3rd and the result will still be
correct because the final value is the 3rd one which incorporates all the input
changes.